1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, it relates to a ferroelectric memory that stores data in a non-volatile manner using a memory cell including a ferroelectric capacitor and a transistor.
2. Description of the Related Art
A ferroelectric memory (FeRAM) is a semiconductor memory device using hysteresis properties of a ferroelectric capacitor. FeRAM can store data in a nonvolatile manner based on two different polarization strengths of a ferroelectric material. In general, a memory cell in a conventional ferroelectric memory adopts a similar architecture to DRAM. That is, a paraelectric capacitor in DRAM is replaced with a ferroelectric capacitor, and the ferroelectric capacitor and a transistor are connected in series to form a memory cell (JP2001-250376A). A plurality of such ferroelectric capacitors and transistors are arranged to form a memory cell array. The ferroelectric memory includes a 2 transistor-2 cell scheme (2T/2C scheme) in which data is read from two memory cells, and a 1 transistor-1 cell scheme (1T/1C scheme) in which data is read from one memory cell.
The 1T/1C system selects a word line of the cell to be read, and turns on the select transistor, thereby connecting the memory cell to a bit line. A plate voltage is then applied to a plate line connected to the memory cell, and a voltage is applied across the ferroelectric capacitor included in the memory cell. The charge from the ferroelectric capacitor is read to the bit line. The bit line forms a bit-line pair with another bit line (complementary bit line). The complementary bit line is applied with a reference potential from a reference potential generating circuit. A sense amplifier amplifies the difference between the bit-line pair potentials. The difference in the charge read to the bit-line pair thus represents an amount of signal.
The 1T/1C scheme is advantageous for high integration, but because the amount of signal is half that of the 2T/2C scheme, increasing the amount of signal is a problem. Known as a way of increasing the amount of signal in the 1T/1C scheme is, for example, a technique as disclosed in JP2001-319472A.
In the technique of this JP2001-319472A, after the voltage is applied across the ferroelectric capacitor and the signal corresponding to data is read to the bit line, and prior to operation of a sense amplifier circuit, control is performed to reduce (step down) the voltage of the bit line to which the signal is read. The step down operation causes an absolute value of the amount of the signal to decrease in both data “1” and data “0”. However, as a result of the latter decrement being larger than that of the former, the difference in the amount of signal can be increased. The technique of this JP2001-319472A has some effectiveness as a way of increasing the difference in the amount of signal.